http://www.eng.auburn.edu/department/ee/mgc/vhdl.html

http://www.eng.auburn.edu/department/ee/mgc/vhdl.html

VHDL MINI-REFERENCE

See the VHDL Language Reference Manual (VLRM) for Additional Details

The following Mini-Reference can be divided into the following parts:

I. Primary Design Unit Model Structure
A. Entity Declaration Format
B. Architecture
II. Packages
A. Declaration and Libraries
B. Identifiers, Numbers, Strings, and Expressions
C. Data Types
D. Objects: Signals, Constants, and Variables
E. Concurrent Statements
1) Signal Assignment
2) Process Statement
3) Block Statement
4) Procedure Statement
5) Component Instantiation
6) Concurrent Assertion
7) Generate Statement
F. Sequential Statements
1) Wait Statement
2) Signal Assignment
3) Variable Assignment
4) Procedure Call
5) Conditional Statements
6) Loop Statements
7) Procedure Statement
8) Function Statement
G. Other IEEE "std.logic" Functions
H. Object Attributes
I. The TEXTIO Package